1#ifndef KEST_INT_FPGA_H_
2#define KEST_INT_FPGA_H_
4#define KEST_FPGA_SAMPLE_RATE 44100
8#define COMMAND_BEGIN_PROGRAM 1
9#define COMMAND_WRITE_BLOCK_INSTR 2
10#define COMMAND_WRITE_BLOCK_REG_0 3
11#define COMMAND_WRITE_BLOCK_REG_1 4
12#define COMMAND_ALLOC_DELAY 5
13#define COMMAND_END_PROGRAM 10
14#define COMMAND_SET_INPUT_GAIN 11
15#define COMMAND_SET_OUTPUT_GAIN 12
16#define COMMAND_UPDATE_BLOCK_REG_0 13
17#define COMMAND_UPDATE_BLOCK_REG_1 14
18#define COMMAND_COMMIT_REG_UPDATES 15
19#define COMMAND_ALLOC_FILTER 16
20#define COMMAND_WRITE_FILTER_COEF 17
21#define COMMAND_UPDATE_FILTER_COEF 18
22#define COMMAND_COMMIT_FILTER_COEF 19
24#define SPI_RESPONSE_OK 0
25#define SPI_RESPONSE_INITIALISING 1
26#define SPI_RESPONSE_PROGRAMMING 2
27#define SPI_RESPONSE_REJECTED 3
28#define SPI_RESPONSE_TIMEOUT 4
30#define KEST_FPGA_N_BLOCKS 256
32#if KEST_FPGA_N_BLOCKS > 256
33 #define KEST_FPGA_BLOCK_ADDR_BYTES 2
36 #define KEST_FPGA_BLOCK_ADDR_BYTES 1
40#define KEST_FPGA_DATA_WIDTH 16
41#define KEST_FPGA_FILTER_WIDTH 18
42#define KEST_FPGA_DATA_BYTES (KEST_FPGA_DATA_WIDTH / 8)
44#if KEST_FPGA_DATA_WIDTH == 16
46#elif KEST_FPGA_DATA_WIDTH == 24
void kest_fpga_set_input_gain(float gain_db)
char * kest_fpga_command_to_string(int command)
int kest_fpga_batch_append_16(kest_fpga_transfer_batch *seq, uint16_t x)
int kest_fpga_send_byte(uint8_t byte)
uint8_t kest_fpga_block_addr_t
void kest_fpga_set_output_gain(float gain_db)
int kest_fpga_batch_append(kest_fpga_transfer_batch *seq, uint8_t x)
int kest_send_byte_to_fpga(uint8_t byte)
int kest_send_bytes_to_fpga(uint8_t *buf, int n)
int kest_fpga_batch_append_24(kest_fpga_transfer_batch *seq, uint32_t x)
void kest_free_fpga_transfer_batch(kest_fpga_transfer_batch batch)
uint8_t kest_fpga_read_byte()
void kest_fpga_commit_reg_updates()
int kest_fpga_batch_append_32(kest_fpga_transfer_batch *seq, uint32_t x)
kest_fpga_transfer_batch kest_new_fpga_transfer_batch()
int16_t kest_fpga_sample_t
int kest_fpga_transfer_batch_send(kest_fpga_transfer_batch batch)